• Home
  • Features
  • Pricing
  • Docs
  • Announcements
  • Sign In

lluckydog / Verilog-OJ / 1379555401 / 1
55%
master: 55%

Build:
DEFAULT BRANCH: master
Ran 25 Oct 2021 04:30AM UTC
Files 70
Run time 4s
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst

25 Oct 2021 04:30AM UTC coverage: 54.244%. Remained the same
1379555401.1

push

github-actions

luckyydog
change url

1029 of 1897 relevant lines covered (54.24%)

0.54 hits per line

Source Files on job 1379555401.1
  • Tree
  • List 0
  • Changed 1
  • Source Changed 1
  • Coverage Changed 0
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
  • Back to Build 1379555401
  • a5c61536 on github
  • Prev Job for on master (#1378025798.1)
  • Next Job for on master (#1384875281.1)
STATUS · Troubleshooting · Open an Issue · Sales · Support · CAREERS · ENTERPRISE · START FREE · SCHEDULE DEMO
ANNOUNCEMENTS · TWITTER · TOS & SLA · Supported CI Services · What's a CI service? · Automated Testing

© 2026 Coveralls, Inc