3
36%
master: 36%

Ran 28 May 2021 09:59PM UTC

Files 1902

Run time 2min

Badge

Committed 02 Apr 2021 05:49PM UTC coverage: 35.781%. Remained the same

Build Type

cron

travis-ci

Committed by

Commit Message

Merge pull request #68 from SRI-CSL/nra

Extensions to use SMT modulo models and interpolation from latest Yices2

Run Details

5910 of 16517 relevant lines covered (35.78%)

15411.49 hits per line