1
87%
master: 87%

Ran 24 Oct 2020 08:32AM UTC

Files 184

Run time 13s

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Committed 24 Oct 2020 08:29AM UTC coverage: 87.025% (-0.002%) from 87.027%

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push

travis-ci

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Commit Message

Merge pull request #2672 from masatake/systemverilog-remove-symtab

SystemVerilog,refactor: remove unused code about type tracker

Run Details

36158 of 41549 relevant lines covered (87.02%)

13403.28 hits per line