lluckydog / Verilog-OJ / 82 / 1
55%
master: 55%

DEFAULT BRANCH: master
Ran
Files 57
Run time 4s
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Rst
coverage: 58.964%. Remained the same
82.1

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travis-ci

libreliu 
Working SYNTHSIM

865 of 1467 relevant lines covered (58.96%)

0.59 hits per line

Source Files on job 82.1