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leonardt 
Fix inline blacklist logic for recursive case

Before if we had a module such as:
```verilog
module test_module (
    input [4:0] i1,
    input [4:0] i2,
    output [3:0] o0,
    output [3:0] o1,
    output [3:0] o2
);
wire [4:0] x;
wire [4:0] y;
wire [4:0] h;
wire [4:0] g;
assign x = i1 + i2;
assign h = i1 - i2;
assign g = h;
assign o0 = x[3:0];
assign y = i1;
assign o1 = y[3:0];
assign o2 = g[3:0];
endmodule;
```

We would get

```verilog
module test_module (
    input [4:0] i1,
    input [4:0] i2,
    output [3:0] o0,
    output [3:0] o1,
    output [3:0] o2
);
wire [4:0] x;
wire [4:0] h;
assign x = i1 + i2;
assign o0 = x[3:0];
assign o1 = i1[3:0];
assign o2 = (i1 - i2)[3:0];
endmodule;
```

Notice the (i1 - i2) is inlined into the slice node, which is invalid.

The reason was the blacklisting logic was not recursively checking
identifiers.  That is, when we encounter a slice, we let a an
identifier be inlined for another identifier into the contents of the
slice.  However, this is problematic when the identifier being inlined
will in turn be replaced by something which may not be valid (e.g. an
expression).  So, we improve the blacklisting logic to recursively check
inlined identifiers until we encounter an invalid driver of inlining.
At this point, we blacklist the current identifier so that it will not
be eventually inlined into the slice/index node.

So, for the above example we now get
```verilog
module test_module (
    input [4:0] i1,
    input [4:0] i2,
    output [3:0] o0,
    output [3:0] o1,
    output [3:0] o2
);
wire [4:0] x;
wire [4:0] h;
assign x = i1 + i2;
assign h = i1 - i2;
assign o0 = x[3:0];
assign o1 = i1[3:0];
assign o2 = h[3:0];
endmodule;
```

1075 of 1094 relevant lines covered (98.26%)

97.31 hits per line

Source Files on job 535.2 (MATRIX_EVAL="GCOV=gcov")