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master: 98%

Ran 07 Jan 2020 01:11PM UTC

Files 268

Run time 13s

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Committed 07 Jan 2020 12:59PM UTC coverage: 97.99% (-0.001%) from 97.991%

Job # NAME="unix coverage build and tests"

Build Type

push

travis-ci

Committed by

dpgeorge

Commit Message

stm32/boards/PYBD: Change RTC asynch prediv from 1 to 4.

This change has the following effects:
- Reduces the resolution of the RTC sub-second counter from 30.52us to
  122.07us.
- Allows RTC.calibration() to now support positive values (as well as
  negative values).
- Reduces VBAT current consumption in standby mode by a small amount.

For general purpose use 122us resolution of the sub-second counter is
good enough, and the benefits of full range calibration and minor reduction
in VBAT consumption are worth the change.

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18871 of 19258 relevant lines covered (97.99%)

373178.42 hits per line

micropython / micropython / 12253 / 3
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master: 98%

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