SiLab-Bonn / basil / 1175 / 1
32%
master: 32%

LAST BUILD BRANCH: new_bus_interface
DEFAULT BRANCH: master
Ran
Files 71
Run time 5s
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coverage: 32.163% (+0.08%) from 32.085%
1175.1

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laborleben 
REG: fix not-equal (!=) -1 in Verilog code

1392 of 4328 relevant lines covered (32.16%)

0.32 hits per line

Source Files on job 1175.1