caleb531 / connect-four / 510 / 3
89%
master: 88%

LAST BUILD BRANCH: main
DEFAULT BRANCH: master
Ran
Files 41
Run time 2s
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Rst
coverage: 89.305% (+0.1%) from 89.186%
510.3

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travis-ci

caleb531 
Ensure that pending chip alignment's are in sync at the end

There doesn't appear to be any noticeable jitter, and the diagonal chip
bug is no longer an issue thanks to dd4912d.

169 of 231 branches covered (73.16%)

Branch coverage included in aggregate %.

1167 of 1265 relevant lines covered (92.25%)

4440.7 hits per line

Source Files on job 510.3