Bo-Yuan-Huang / ILAng / 637 / 1
86%
master: 86%

DEFAULT BRANCH: master
Ran
Files 99
Run time 4s
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst
coverage: 86.552% (+0.1%) from 86.407%
637.1

push

travis-ci

web-flow 
Merge pull request #113 from zhanghongce/master

Verilog Verification Target Gen Update -- Now it can handle verilog signal width that involves computation among verilog parameters

8856 of 10232 relevant lines covered (86.55%)

26836.92 hits per line

Source Files on job 637.1