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hriener / lorina / 148 / 1
82%
master: 82%

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Files 18
Run time 2min
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coverage: 85.814% (-0.01%) from 85.826%
COMPILER=g++-7 COVERAGE=ON

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Merge pull request #14 from hriener/verilog_writer

Verilog writer

1101 of 1283 relevant lines covered (85.81%)

46.65 hits per line

Source Files on job 148.1 (COMPILER=g++-7 COVERAGE=ON)