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Ran 08 Jul 2026 01:27AM UTC

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Committed 08 Jul 2026 01:24AM UTC coverage: 92.425%. Remained the same

Job # 28910646370.1

Build Type

push

github

Committed by

arnavsacheti

Commit Message

Add --clk-src and opt-in --gate-signals; merge APB cpuifs (0.7.0b4)

Beta 4 of the 0.7.0 series. Highlights since 0.7.0b3:

- --clk-src {cpuif,design}: select where the decoder gets clock/reset.
  New default "design" drops PCLK/PRESETn (ACLK/ARESETn) from the bus
  and adds top-level clk/rst ports (#72).
- Downstream APB broadcast-signal gating is now opt-in via
  --gate-signals; default fans signals out unmodified for a shorter
  master-to-slave datapath (#74). Reverses the always-on gating that
  headlined 0.7.0b3.
- APB3/APB4 cpuif implementations merged into a shared cpuif/apb
  package; deep import paths preserved via re-export shims (#66).
- Decode boundaries fixed below rolled array ancestors (#71).
- DesignScanner perf: per-node fact caching and inline RDL parameter
  tracing (#63, #64).
- AXI4-Lite per-slave back-pressure limitation documented (#69).

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GMyMaHGbpgrU6YvFVTjKYW

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