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test: add cross-block integration suite verifying end-to-end decoder flow (#68)

* test: add cross-block integration suite verifying end-to-end decoder flow

The existing unit tests exercise each generator class in isolation and
mostly assert on substrings of the output. This adds tests/integration/,
which exports whole multi-block designs and checks that the generated
module works as a coherent system:

- A Python evaluator for the generated address decoder (helpers.route)
  feeds concrete addresses through the parsed if/else + for-loop
  structure and asserts every register address selects its enclosing
  block (and gap addresses select nothing), with expectations derived
  from the compiled SystemRDL tree rather than hardcoded strings.
- Cross-generator consistency checks: module ports, the cpuif_sel
  struct, fanout, fanin, decode targets, and package localparams must
  all agree on the same set of downstream blocks, for all six CPUIF
  flavors (APB3/APB4/AXI4-Lite, interface and flat).
- Hierarchy coverage: 2D arrays, regfile decode boundaries at
  max_decode_depth 2 and 0, sibling blocks, and cpuif_unroll.

Building the suite surfaced four real cross-generator bugs, documented
as strict xfails so they flip loudly when fixed:
- max_decode_depth=2 with sibling addrmap blocks emits duplicate leaf
  ports while decode/fanout reference undeclared mid-level ports
- registers shallower than max_decode_depth are decoded but dropped
  from the port list
- an arrayed register at the decode boundary is decoded as its whole
  parent regfile (invalid struct-to-bit assignment)
- cpuif_unroll=True unrolls ports but fanout still drives the rolled
  interface array

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01TMFtybV4NhYwyMKNwVLkGn

* fix: make all generator stages agree on the decode boundary

Fixes the four cross-generator bugs surfaced by the integration suite
(tests/integration), plus one latent bug... (continued)

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Source Files on job 28823325135.1