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perf(mining): pipelined HW SHA + raw MMIO on D0 (TA-367 Phase B+C) (#394)

restructures the classic ESP32 (DPORT bus) SHA hot loop to overlap CPU
fill with HW peripheral compute. After each SHA_START/CONTINUE/LOAD
trigger, the CPU immediately begins filling the next block's TEXT
slots while the peripheral works in parallel. AxeHub's CYCLE PROBE
on the same silicon proved this is safe at grace=0.

also drops the DPORT_REG_WRITE/READ macros for raw volatile pointer
access (the macros add serialization barriers the SHA peripheral
doesn't need; we already hold sha256_hw_acquire across the job).

eliminates the per-nonce DPORT_INTERRUPT_DISABLE/RESTORE pair — the
erratum it guarded against required cross-task SHA contention, which
cannot happen while we hold the SHA acquire lock.

inlines the hot loop into mine_nonce_range so the compiler can
schedule fill instructions inside the peripheral busy-wait window.

expected hashrate: 212 -> ~340 kH/s on esp32-wroom32. the non-inlined
sha256_hw_dport_per_nonce remains as the SW-vs-HW lockstep test's
reference path.

Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>

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