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Add JIT backend specifications: BPF ISA -> x86-64 and ARM64 mappings (#779)

* Add JIT backend specifications: BPF ISA → x86-64 and ARM64

Extract complete instruction-level mappings from the existing JIT
compiler source code to serve as reference specifications for future
backend implementations (RISC-V, MIPS).

docs/specs/jit-x86-64.md (1039 lines, 43KB):
  - Register mapping for System V and Win64 ABIs
  - All 13 BPF instruction categories → x86-64 sequences
  - Prologue/epilogue for Basic and Extended JIT modes
  - Constant blinding, retpoline, W^X security features
  - Helper dispatch (static table + dynamic dispatcher)
  - Patchable target system and fixup algorithm
  - Platform differences (System V vs Win64)

docs/specs/jit-arm64.md (1006 lines, 44KB):
  - BPF → ARM64 register mapping (R0→x5, R1-R5→x0-x4)
  - All 13 BPF instruction categories → ARM64 sequences
  - LDXR/STXR atomic operation loops
  - ARM64-specific constraints (immediate encoding, offset
    ranges, branch limits)
  - Constant blinding coverage analysis
  - MOVZ/MOVK sequences for large immediates

Both documents cite source file:line for every mapping and
cross-reference REQ-UBPF-ISA-* IDs from isa-reconciliation.md.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

* Address PR #779 review comments

x86-64 JIT spec:
- Fix all 11 cross-reference IDs from numeric format (REQ-UBPF-ISA-005)
  to correct categorical format (REQ-UBPF-ISA-ALU-001, DIV-003, etc.)
  matching isa-reconciliation.md

ARM64 JIT spec:
- Fix atomic pseudocode: address base uses x26 (not x25) to avoid
  aliasing with STXR status register (W25), matching the actual
  implementation logic in ubpf_jit_arm64.c:771-772
- Strengthen constant blinding discrepancy note: add recommendation
  to update vm/inc/ubpf.h header in a follow-up change

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

* Fix technical inaccuracies in JIT backend specs

x86-64:
- R12 note: clarify that... (continued)

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