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Qiskit / qiskit / 18653334578 / 1
88%
main: 88%

Build:
Build:
LAST BUILD BRANCH: opt-loop-logic
DEFAULT BRANCH: main
Ran 20 Oct 2025 02:04PM UTC
Files 871
Run time 28s
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20 Oct 2025 01:19PM UTC coverage: 88.264% (+0.004%) from 88.26%
18653334578.1

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Fix schedule analysis passes with empty circuits (#15147)

Internally the passes look for the time-unit type of the first operation
in the circuit, to dispatch to wall-time or clock-cycle handlers.  This
caused trouble if there _were_ no durations, even though the circuit is
trivially scheduled.

93236 of 105633 relevant lines covered (88.26%)

1159257.39 hits per line

Source Files on job 18653334578.1
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