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Ran 11 Aug 2016 01:37PM UTC

Files 175

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Committed 11 Aug 2016 01:22PM UTC coverage: 70.369% (+0.02%) from 70.354%

Job # 436.2

Build Type

push

travis-ci

Committed by

web-flow

Commit Message

The vivado path changes and vendor primitive fix. (#46)

* Fixed VHDL conversion via rhea.build.toolflow.convert, fixed a typo, fixed spacing

* Added 'ticks' property to Clock() to retrieve the ratio of the clocks ticks to simulation ticks

* Added Clock.delay() to allow for easy delaying for a certain number of ticks of user clock signals

* Parameter checking and setting ticks when hticks is overridden in Clock.gen()

* Whitespace and @todo comment / question

* Removed a comment and delay()

* Fix for https://github.com/cfelton/rhea/issues/41, escapes backspaces as well as quoting file paths (so paths with spaces in them will also work

* Fix for Vivado 2016.2 toolchain not launching on Windows 10.   (Needed to specify full binary 'vivado.bat' for windows to find it)

* Changed quoting style per @cfelton's request

* Initial definitions for Digilent CModA7_15T & CModA7_35T

* Added uart to cmoda7, and commented in remaining constraints for future reference

* Added pmod_je (standard pmod) definition to zybo board.  Hardware verified

* Added cellular ram part reference and datasheet link

* enable zybo in build make file

* the verilog_code needs to be attached to a block before it is instantiated

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