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Ran 17 Oct 2023 02:27AM UTC

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Committed 17 Oct 2023 02:11AM UTC coverage: 68.331% (-0.02%) from 68.347%

Job # 6541658484.1

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github

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Commit Message

Fix: CXL memory traffic generator bandwidth numbers (#3025)

* Fix: CXL memory traffic generator bandwidth numbers

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>

* fix: check read, write, loop count range

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>

* fix: loop count default value

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>

* fix: build error set cmd default string value

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>

* fix: code review comments

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>

---------

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>

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