meetshah1995 / riscv
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master: 91%

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Merge pull request #9 from srivatsan-ramesh/dev

partial verilator_top module

112 of 112 new or added lines in 6 files covered. (100.0%)

1037 of 2097 relevant lines covered (49.45%)

0.49 hits per line

Relevant lines Covered
2097 RELEVANT LINES 1037 COVERED LINES
0.49 HITS PER LINE
Source Files on dev
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
74 dev Merge pull request #9 from srivatsan-ramesh/dev partial verilator_top module push web-flow travis-ci pending completion  
73 dev top_level runs without error Pull #9 web-flow travis-ci pending completion  
72 dev Merge branch 'dev' of github.com:meetshah1995/riscv into dev push meetshah1995 travis-ci pending completion  
71 dev verilator_top completed Pull #9 web-flow travis-ci pending completion  
70 dev Add documentation for the core push meetshah1995 travis-ci pending completion  
69 dev fixed some syntax errors in dp_hasti_sram Pull #9 web-flow travis-ci pending completion  
63 dev fixed some syntax errors in vscale_core Pull #8 web-flow travis-ci pending completion  
62 dev Add main assembly module push meetshah1995 travis-ci pending completion  
61 dev Change to hex literals and use intbv push meetshah1995 travis-ci pending completion  
60 dev Use instances in csr_file push meetshah1995 travis-ci pending completion  
See All Builds (52)