meetshah1995 / riscv / 74
49%
master: 91%

LAST BUILD BRANCH: dev
DEFAULT BRANCH: master
Ran
Jobs 1
Files 25
Run time 2s
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Merge pull request #9 from srivatsan-ramesh/dev

partial verilator_top module

112 of 112 new or added lines in 6 files covered. (100.0%)

1037 of 2097 relevant lines covered (49.45%)

0.49 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
100.0
 riscv/pipeline.py
3
100.0
 riscv/core.py
6
100.0
 riscv/csr_file.py
11
100.0
 riscv/top_level.py
44
100.0
 riscv/verilator_top.py
47
100.0
 riscv/dp_hasti_sram.py

Uncovered Existing Lines

Lines Coverage ∆ File
1
100.0
 riscv/csr_file.py
1
100.0
 riscv/top_level.py
3
100.0
 riscv/PC_mux.py
3
100.0
 riscv/immediate_gen.py
Jobs
ID Job ID Ran Files Coverage
1 74.1 0
49.45
 Travis Job 74.1
Source Files on build 74
Detailed source file information is not available for this build.