Qiskit / qiskit
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LAST BUILD ON BRANCH mergify/bp/stable/2.2/pr-15147
branch: mergify/bp/stable/2.2/pr-15147
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coverage: 88.423% (+0.02%) from 88.407%
18654176170

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mergify[bot] 
Fix schedule analysis passes with empty circuits (#15147)

Internally the passes look for the time-unit type of the first operation
in the circuit, to dispatch to wall-time or clock-cycle handlers.  This
caused trouble if there _were_ no durations, even though the circuit is
trivially scheduled.

(cherry picked from commit cd49fb74b)

46 of 62 new or added lines in 2 files covered. (74.19%)

7 existing lines in 2 files now uncovered.

92364 of 104457 relevant lines covered (88.42%)

550052.99 hits per line

Relevant lines Covered
104457 RELEVANT LINES 92364 COVERED LINES
550052.99 HITS PER LINE
Source Files on mergify/bp/stable/2.2/pr-15147

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
18654176170 mergify/bp/stable/2.2/pr-15147 Fix schedule analysis passes with empty circuits (#15147) Internally the passes look for the time-unit type of the first operation in the circuit, to dispatch to wall-time or clock-cycle handlers. This caused trouble if there _were_ no durations... push mergify[bot] github
88.42
18654029552 mergify/bp/stable/2.2/pr-15147 Fix schedule analysis passes with empty circuits (#15147) Internally the passes look for the time-unit type of the first operation in the circuit, to dispatch to wall-time or clock-cycle handlers. This caused trouble if there _were_ no durations... push mergify[bot] github
88.42
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