Alan-Jowett / ubpf
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Add ISA-verified MIPS64r6 JIT backend specification (#782)

* Add proposed MIPS64r6 JIT backend specification

Proposed BPF ISA to MIPS64 Release 6 instruction mapping, following
the same template structure as the existing x86-64 and ARM64 specs.
All mappings are marked [PROPOSED] — no implementation exists yet.

Key design decisions:
- Target MIPS64r6 (compact branches, native DDIV/DMOD, no delay slots)
- N64 ABI with BPF R1-R5 -> \-\ (zero-cost helper marshaling)
- BPF R0 -> \ (natural return register)
- BPF R6-R10 -> \-\ (callee-saved)

Key challenges identified:
- 32-bit ALU zero-extension: MIPS64 sign-extends 32-bit results,
  BPF requires zero-extension (needs explicit DINSU or DSLL32+DSRL32)
- No store-immediate instruction (all ST_IMM need temp register)
- 16-bit immediate limit (64-bit values need 6-instruction sequences)
- No PC-relative data access (unlike x86-64 RIP-relative)
- Constant blinding cost: 13 instructions per blinded 64-bit load
- Cache coherence: may need synci+sync after mprotect

5 design decisions flagged for implementer resolution.
Addresses iovisor/ubpf#182.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

* Address PR #781 review comments

- Fix static dispatch: remove bogus DSLL \,\,3 (always 0),
  use DADDIU for index offset computation
- Fix dynamic dispatch: OR cannot load immediate, use LI pseudo-op
- Reconcile §3.6 vs §8.2: clarify that BPF offsets always fit in
  16-bit MIPS offset; large-offset sequence is for non-BPF data only
- Fix BC branch range: ±33M instructions / ±128MB (not ±256M)
- Fix helper table base: document need for dedicated base register
  instead of ambiguous \ reference
- Fix prologue: set \ = \ after saving (not unused save/restore)

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

* Regenerate MIPS64r6 JIT spec from formal ISA reference

Replace training-data-based MIPS spec with one verified against
the MIPS64 Architecture for Programmers Vol II, Re... (continued)

6586 of 8255 relevant lines covered (79.78%)

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Relevant lines Covered
8255 RELEVANT LINES 6586 COVERED LINES
535941.86 HITS PER LINE
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Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
25404271706 main Add ISA-verified MIPS64r6 JIT backend specification (#782) * Add proposed MIPS64r6 JIT backend specification Proposed BPF ISA to MIPS64 Release 6 instruction mapping, following the same template structure as the existing x86-64 and ARM64 specs. ... push web-flow github
79.78
25345460906 main Add ISA-verified MIPS64r6 JIT backend specification (#782) * Add proposed MIPS64r6 JIT backend specification Proposed BPF ISA to MIPS64 Release 6 instruction mapping, following the same template structure as the existing x86-64 and ARM64 specs. ... push web-flow github
79.78
25291364368 main Add ISA-verified MIPS64r6 JIT backend specification (#782) * Add proposed MIPS64r6 JIT backend specification Proposed BPF ISA to MIPS64 Release 6 instruction mapping, following the same template structure as the existing x86-64 and ARM64 specs. ... push web-flow github
79.78
25262319635 main Add ISA-verified MIPS64r6 JIT backend specification (#782) * Add proposed MIPS64r6 JIT backend specification Proposed BPF ISA to MIPS64 Release 6 instruction mapping, following the same template structure as the existing x86-64 and ARM64 specs. ... push web-flow github
79.78
25234379180 main Add ISA-verified MIPS64r6 JIT backend specification (#782) * Add proposed MIPS64r6 JIT backend specification Proposed BPF ISA to MIPS64 Release 6 instruction mapping, following the same template structure as the existing x86-64 and ARM64 specs. ... push web-flow github
79.78
25190832903 main Add ISA-verified MIPS64r6 JIT backend specification (#782) * Add proposed MIPS64r6 JIT backend specification Proposed BPF ISA to MIPS64 Release 6 instruction mapping, following the same template structure as the existing x86-64 and ARM64 specs. ... push web-flow github
79.78
25135701377 main Add ISA-verified MIPS64r6 JIT backend specification (#782) * Add proposed MIPS64r6 JIT backend specification Proposed BPF ISA to MIPS64 Release 6 instruction mapping, following the same template structure as the existing x86-64 and ARM64 specs. ... push web-flow github
79.78
25079449616 main Add ISA-verified MIPS64r6 JIT backend specification (#782) * Add proposed MIPS64r6 JIT backend specification Proposed BPF ISA to MIPS64 Release 6 instruction mapping, following the same template structure as the existing x86-64 and ARM64 specs. ... push web-flow github
79.78
25021168207 main Add ISA-verified MIPS64r6 JIT backend specification (#782) * Add proposed MIPS64r6 JIT backend specification Proposed BPF ISA to MIPS64 Release 6 instruction mapping, following the same template structure as the existing x86-64 and ARM64 specs. ... push web-flow github
79.78
24967457439 main Add ISA-verified MIPS64r6 JIT backend specification (#782) * Add proposed MIPS64r6 JIT backend specification Proposed BPF ISA to MIPS64 Release 6 instruction mapping, following the same template structure as the existing x86-64 and ARM64 specs. ... push web-flow github
79.78
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