drom / irtl / 28989074554

91%

Build Type

push

github

Committed by drom

Commit Message

feat(emit): complete FIRRTL primop coverage + add Verilog-native ops

outdated validif removed.

Both emitters silently mishandled most ops: Verilog fell through to
`[object Object]`, FIRRTL to a self-assign `x <= x`. Only bitwise,
reduction, buf, literal, repeat, and bits actually emitted.

- Verilog emitter: emit arithmetic (+ - * / %), comparison
  (< <= > >= == !=), shifts, mux (? :), casts ($signed/$unsigned),
  pad/head/tail (width-aware slice/zero-extend). Unknown op now throws
  instead of emitting garbage.
- FIRRTL emitter: extend fold-binary/unary sets to the full primop list;
  add mux and param ops (shl shr head tail pad). Unknown op now throws.
- Add missing FIRRTL casts to IRTL: asClock, asAsyncReset, asReset.

Also add Verilog-native ops beyond the FIRRTL primop set:
- signed-aware right shift: shr/dshr emit `$signed(x) >>> n` when the
  operand is signed, else logical `>>` (fixes an arithmetic-shift bug).
- reductions nandr/norr/xnorr, bitwise xnor, logical land/lor/lnot.
  These have no FIRRTL primop, so the FIRRTL emitter lowers them to
  equivalent primop trees (e.g. xnor -> not(xor(...))).

README: document the op set, Verilog operator mapping, signed-shift and
lowering semantics; fix a stale quick-start output (4'd0 -> 4'd15).

Coverage Stats

426 of 544 branches covered (78.31%)

Branch coverage included in aggregate %.

89 of 139 new or added lines in 3 files covered. (64.03%)

3 existing lines in 2 files now uncovered.

1691 of 1800 relevant lines covered (93.94%)

36.38 hits per line