arnavsacheti / PeakRDL-BusDecoder / 28911814161

92%

Build Type

push

github

Committed by web-flow

Commit Message

feat(cpuif): add --apb-buffer for APB slave-side I/O register slice (#75)

New exporter option (and CLI flag) inserts a single-flop register
slice on the APB slave-side I/O. Modes:

- "none" (default): no buffering
- "in":   register slave-side inputs  (PSEL/PENABLE/PWRITE/PADDR/
                                      PWDATA/PSTRB/PPROT)
- "out":  register slave-side outputs (PRDATA/PREADY/PSLVERR)
- "both": register both directions

Implementation:
- ``APBCpuifBase.signal()`` redirects slave-side references to
  ``apb_in_<X>``/``apb_out_<X>`` wires when the corresponding
  direction is buffered. Master-side fanout is unchanged.
- ``APBCpuifBase.apb_buffer_block()`` emits the wire declarations
  and (for the buffered direction) a single ``always_ff`` that
  flops on/off the slave port.
- The APB handshake is preserved by APB's PREADY-stretching
  semantics: each buffered direction adds one cycle to the access
  phase, which is allowed by the protocol.

Validation:
- ``apb_buffer != "none"`` requires ``clk_src=design`` (the flops
  use the design clk/rst).
- Non-APB cpuifs reject the option via
  ``BaseCpuif.supports_apb_buffer``.

Builds on the top-level ``clk``/``rst`` ports added by --clk-src
(#72), since the buffer flops use them. This is the foundation for
upcoming pipelining support.



Claude-Session: https://claude.ai/code/session_01GMyMaHGbpgrU6YvFVTjKYW

Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

Coverage Stats

85 of 88 new or added lines in 5 files covered. (96.59%)

1 existing line in 1 file now uncovered.

1598 of 1725 relevant lines covered (92.64%)

0.93 hits per line