arnavsacheti / PeakRDL-BusDecoder / 28909883490

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Commit Message

feat(cpuif): add --clk-src {cpuif,design} flag (#72)

* feat(cpuif): add --clk-src {cpuif,design} flag

Adds an exporter option (and CLI flag) to select where the bus
decoder gets its clock and reset:

- clk_src=cpuif: clk/reset are bundled with the CPU interface. The
  slave bus carries protocol-defined clock/reset (PCLK/PRESETn for
  APB, ACLK/ARESETn for AXI4-Lite) and the decoder fans them out to
  each master interface.

- clk_src=design (default): the CPU interface carries no clk/reset.
  The module exposes top-level `clk` and `rst` ports; the design
  itself is responsible for distributing clock/reset to downstream
  slaves. This is also the foundation for adding pipelining support.

Stacked on top of the cpuif refactor (#66).

Replaces the stale draft in #32; this version targets the merged
APB3/APB4 cpuif, ports cleanly to the new declarative interface
layer, and drops the unrelated APB4 assertion removal that the
original PR bundled in.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

* test: wire top-level clk/rst through the Verilator intf wrapper

In the default clk_src="design" mode the DUT gained top-level clk/rst
ports; the generated interface wrapper left those pins unconnected and
Verilator fails the intf smoke suites on PINMISSING. Expose them as
wrapper inputs and wire them through (include_top_clk_rst=False for
future clk_src="cpuif" DUTs, which have no such ports).

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GMyMaHGbpgrU6YvFVTjKYW

---------

Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

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34 of 35 new or added lines in 8 files covered. (97.14%)

1 existing line in 1 file now uncovered.

1509 of 1632 relevant lines covered (92.46%)

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