SRI-CSL / yices2 / 28824774146
71%
master: 71%

LAST BUILD BRANCH: fix-bv64-interval-abstraction-ub
DEFAULT BRANCH: master
Ran
Jobs 1
Files 496
Run time 2min
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coverage: 71.193% (+0.002%) from 71.191%
28824774146

Pull #653

github

web-flow 
Merge 3055a1b04 into d7a1fdfda
Pull Request #653: Make the SMT-LIB 2.6 "" string escape the default (#417)

4 of 4 new or added lines in 2 files covered. (100.0%)

95520 of 134170 relevant lines covered (71.19%)

1620975.52 hits per line

Jobs
ID Job ID Ran Files Coverage
1 28824774146.1 496
71.19
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Source Files on build 28824774146