• Home
  • Features
  • Pricing
  • Docs
  • Announcements
  • Sign In

SRI-CSL / yices2 / 28824367373
71%
master: 71%

Build:
Build:
LAST BUILD BRANCH: fix-bv64-interval-abstraction-ub
DEFAULT BRANCH: master
Ran 06 Jul 2026 09:43PM UTC
Jobs 1
Files 496
Run time 2min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst

06 Jul 2026 09:25PM UTC coverage: 71.188% (-0.003%) from 71.191%
28824367373

Pull #653

github

web-flow
Merge a967747fc into d7a1fdfda
Pull Request #653: Make the SMT-LIB 2.6 "" string escape the default (#417)

3 of 3 new or added lines in 2 files covered. (100.0%)

15 existing lines in 1 file now uncovered.

95513 of 134170 relevant lines covered (71.19%)

1621686.68 hits per line

Coverage Regressions

Lines Coverage ∆ File
15
91.8
0.28% src/frontend/smt2/smt2_lexer.c
Jobs
ID Job ID Ran Files Coverage
1 28824367373.1 06 Jul 2026 09:43PM UTC 496
71.19
GitHub Action Run
Source Files on build 28824367373
  • Tree
  • List 496
  • Changed 3
  • Source Changed 3
  • Coverage Changed 2
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
  • Back to Repo
  • Github Actions Build #28824367373
  • Pull Request #653
  • PR Base - master (#28822899525)
STATUS · Troubleshooting · Open an Issue · Sales · Support · CAREERS · ENTERPRISE · START FREE TRIAL · SCHEDULE DEMO
ANNOUNCEMENTS · TWITTER · TOS & SLA · Supported CI Services · What's a CI service? · Automated Testing

© 2026 Coveralls, Inc