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Embed TickCounters in IsrState, eliminate copy boilerplate (#39)

* Embed TickCounters in IsrState, eliminate copy boilerplate

IsrState had 4 loose fields (ten_khz_counter, one_khz_loop_counter,
armed_timeout_count, tim1_arr) that were copied into a temporary
TickCounters on every ISR entry and copied back after. Replace with
an embedded counters: TickCounters field — zero copy, zero copy-back.

Note: ten_khz_counter and one_khz_loop_counter are incremented but
never read in the ISR — they're dead code from the C port where they
drove the 1kHz PID loop divider (now in MainState::tick).

* Add TickCounters::new() constructor, make fields pub(crate)

Replace struct literal construction with TickCounters::new(tim1_arr).
Fields made pub(crate) — only tim1_arr varies, rest always zero.
Add set_tim1_arr() setter and armed_timeout_count() getter for
cross-crate access.

* Delete dead ten_khz_counter and one_khz_loop_counter from TickCounters

Both were incremented every ISR tick but never read. They were the C
firmware's 1kHz PID loop divider counters — in Rust, PID loops run in
MainState::tick() instead, making these ISR counters orphaned.

TickCounters now has only 2 fields: armed_timeout_count and tim1_arr.

* Make TickCounters fields private

* Remove tim1_arr from TickCounters, read from SharedComm directly

tim1_arr was cached in TickCounters but overwritten from SharedComm
every tick — a stale shadow that served no purpose. The ISR now reads
ctx.shared.tim1_arr() into a local variable at tick start.

Firmware publishes initial tim1_arr to SharedComm before enabling
interrupts, so the ISR sees the correct value from the first tick.

TickCounters is now a single field: armed_timeout_count.

* Delete TickCounters struct, inline armed_timeout_count

TickCounters was a single-field wrapper around a u32 counter.
Replace with a plain &mut u32 in MotorContext. Delete the struct,
its constructor, Default impl, and accessor.

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