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Ran 30 Mar 2026 04:45PM UTC

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Committed 30 Mar 2026 04:42PM UTC coverage: 85.116%. Remained the same

Build # 23756278187

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Commit Message

docs: SPICE simulation pipeline specification (#583) (#584)

* docs: SPICE simulation pipeline specification (issue #583)

Spec for automated SPICE simulation from generated schematics:
- Netlist JSON export from sonde-hw build
- SPICE model library (MCP1700, Si2301, ESP32-C3, passives)
- SPICE deck generation for 6 test cases
- ngspice batch runner with assertion evaluation
- CLI: sonde-hw simulate
- MVP: 3 tests (DC op, sleep current, battery divider)

Relates-to: #583

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

* Address review findings on SPICE pipeline spec

- Fix CLI example paths to use repo-root hw/ prefix (HW-SIM-006)
- Clarify Si2301 model uses VTO/KP/RD/RS for Rds_on (HW-SIM-002)
- Fix MCP1700 subcircuit: Breg drives vout_int, Rout connects to vout (HW-SIM-002)
- Change sleep-current assertion to use source: VBAT for SPICE current measurement (HW-SIM-004)
- Replace completed checkmarks with planned indicators in MVP scope

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

---------

Co-authored-by: Alan Jowett <alan.jowett@microsoft.com>
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

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ID	Job ID	Ran	Files	Coverage
1	23756278187.1	30 Mar 2026 04:45PM UTC	77	85.12	GitHub Action Run

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