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MIPS64: Avoid unaligned load in lj_vm_exit_interp.

Thanks to Sergey Kaplun.

(cherry picked from commit 2aec641e0)

MIPS processors originally required all memory accesses to be naturally
aligned. If we use ld instruction to load a double-word from the address
which is word-aligned, MIPS raises the exception SIGBUS. When exiting
the interpreter, if the current function is a fast function, the code in
the `lj_vm_exit_interp()` throws SIGBUS. The pc field for the fast
function points to the word-aligned bytecodes for ASM fast functions,
and PC2PROTO offset is double-word-aligned. The resulting address is
somewhere in the dispatch table. Hence, some (odd-indexed) fast function
access leads to the BUS error. For other architectures the load from
unaligned access is not a problem so there are no exceptions.

This patch prevents unaligned memory access by address loading only
after fast-function checks.

Sergey Kaplun:
* added the description and the test for the problem

Part of tarantool/tarantool#12134

Reviewed-by: Sergey Bronnikov <sergeyb@tarantool.org>
Signed-off-by: Sergey Kaplun <skaplun@tarantool.org>

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