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Implement RFC 9669 MEMSX sign-extension load instructions (#701)

* Initial plan

* Implement RFC 9669 MEMSX sign-extension load instructions

- Added EBPF_MODE_MEMSX (0x80) constant
- Added LDXBSX, LDXHSX, LDXWSX opcodes for sign-extension loads
- Implemented ubpf_mem_load_sx() for VM interpreter
- Added JIT support for x86-64 with emit_load_sx()
- Added JIT support for ARM64 using existing LS_LDRSB/H/W opcodes
- Added instruction validation filters

Co-authored-by: Alan-Jowett <20480683+Alan-Jowett@users.noreply.github.com>

* Add assembler/disassembler support and comprehensive tests for MEMSX

- Added MEM_LOAD_SX_OPS to assembler.py for ldx{b,h,w}sx instructions
- Updated disassembler.py to recognize MEMSX mode (mode 4)
- Fixed x86-64 JIT emit_load_sx for proper 32-bit sign extension
- Added comprehensive test program validating VM and JIT for all MEMSX variants
- All tests pass for byte, halfword, and word sign extensions

Co-authored-by: Alan-Jowett <20480683+Alan-Jowett@users.noreply.github.com>

* Remove test binary from repository

* Fix pointer dereference spacing in ubpf_mem_load_sx

- Fixed spacing in pointer dereferences to avoid precedence issues
- All tests still pass after the fix

Co-authored-by: Alan-Jowett <20480683+Alan-Jowett@users.noreply.github.com>

* Update .gitignore to exclude test binaries and CodeQL artifacts

* Update .gitignore to exclude test binaries and CodeQL artifacts

Co-authored-by: Alan-Jowett <20480683+Alan-Jowett@users.noreply.github.com>

* Fix .gitignore: preserve .vs/ line and add test artifacts separately

- Keep original .vs/ line unchanged
- Add test_memsx and _codeql_detected_source_root on separate lines
- Add explanatory comment for test artifacts

Co-authored-by: Alan-Jowett <20480683+Alan-Jowett@users.noreply.github.com>

* Remove test_memsx.c development artifact

- test_memsx.c was a temporary test file used during development
- Proper tests are in tests/*.data files (ldxbsx.data, ldxhsx.data, ldxw... (continued)

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