Qiskit / qiskit / 18380445167
88%
main: 88%

LAST BUILD BRANCH: unitary-synthesis
DEFAULT BRANCH: main
Ran
Jobs 1
Files 871
Run time 2min
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coverage: 88.242% (+0.02%) from 88.218%
18380445167

Pull #15147

github

web-flow 
Merge cf7e0a9bf into 83b762d31
Pull Request #15147: Fix schedule analysis passes with empty circuits

46 of 62 new or added lines in 2 files covered. (74.19%)

7 existing lines in 4 files now uncovered.

93147 of 105559 relevant lines covered (88.24%)

1164370.63 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
97.06
 0.74% crates/transpiler/src/passes/alap_schedule_analysis.rs
15
81.67
 0.83% crates/transpiler/src/passes/asap_schedule_analysis.rs

Uncovered Existing Lines

Lines Coverage ∆ File
1
81.99
 0.0% crates/circuit/src/parameter/parameter_expression.rs
1
92.4
 -0.1% crates/transpiler/src/passes/unitary_synthesis.rs
2
92.29
 0.77% crates/qasm2/src/lex.rs
3
73.07
 0.08% crates/circuit/src/parameter/symbol_expr.rs
Jobs
ID Job ID Ran Files Coverage
1 18380445167.1 871
88.24
 GitHub Action Run
Source Files on build 18380445167