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cfelton / rhea / 455
57%

Build:
DEFAULT BRANCH: master
Ran 16 Aug 2016 03:42AM UTC
Jobs 3
Files 525
Run time 1min
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455

Pull #54

travis-ci

web-flow
Also removed phantom conversion warning about clockin not being read
Pull Request #54: Remove phantom warnings in verilog conversion related to Xilinx device_clock_mgmt_prim

14087 of 20022 relevant lines covered (70.36%)

0.7 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
24
100.0
/home/travis/virtualenv/python2.7.9/lib/python2.7/site-packages/rhea/vendor/xilinx/device_clock_mgmt.py
24
100.0
/home/travis/virtualenv/python3.5.2/lib/python3.5/site-packages/rhea/vendor/xilinx/device_clock_mgmt.py
24
100.0
/home/travis/virtualenv/python3.4.2/lib/python3.4/site-packages/rhea/vendor/xilinx/device_clock_mgmt.py
Jobs
ID Job ID Ran Files Coverage
1 455.1 16 Aug 2016 03:43AM UTC 0
70.35
Travis Job 455.1
2 455.2 16 Aug 2016 03:42AM UTC 0
70.35
Travis Job 455.2
3 455.3 16 Aug 2016 03:43AM UTC 0
70.38
Travis Job 455.3
Source Files on build 455
Detailed source file information is not available for this build.
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  • Travis Build #455
  • Pull Request #54
  • PR Base - master (#453)
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