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ARM64: Fix LDP code generation. Thanks to Zhongwei Yao. (cherry picked from commit 9493acc1a) When fusing two LDR (STR) instructions to the single LDP (STP) instruction, the arm64 emitter shifts the offset value to encode the immediate. In the case when the offset is negative, the resulting field value exceeds the 7-bit length of the immediate, see [1]. This results in the invalid instruction decoding. This patch fixes this by masking the value with the 7-bit-width mask `0x7f`. Sergey Kaplun: * added the description and the test for the problem [1]: https://developer.arm.com/documentation/ddi0602/2025-03/Base-Instructions/LDP--Load-pair-of-registers- Part of tarantool/tarantool#11278 Reviewed-by: Sergey Bronnikov <sergeyb@tarantool.org> Signed-off-by: Sergey Kaplun <skaplun@tarantool.org> (cherry picked from commit d30d1613f)
5713 of 6046 branches covered (94.49%)
Branch coverage included in aggregate %.
21802 of 23508 relevant lines covered (92.74%)
3834664.24 hits per line
| Lines | Coverage | ∆ | File |
|---|---|---|---|
| 1 |
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-0.05% | src/lj_record.c |
| 2 |
87.89 |
-0.08% | src/lj_crecord.c |
| 3 |
93.09 |
-0.99% | src/lj_ir.c |
| 4 |
78.59 |
-0.23% | src/lj_opt_fold.c |
| ID | Job ID | Ran | Files | Coverage | |
|---|---|---|---|---|---|
| 1 | 15901242617.1 | 89 |
93.1 |
GitHub Action Run |
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