cfelton / rhea / 439
57%

DEFAULT BRANCH: master
Ran
Jobs 3
Files 525
Run time 1304min
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Rst
439

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travis-ci

cfelton 
Removing debug prints from xilinx clock management pll calculations. (#48)

14087 of 20010 relevant lines covered (70.4%)

0.7 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
4
100.0
 /home/travis/virtualenv/python3.4.2/lib/python3.4/site-packages/rhea/vendor/xilinx/device_clock_mgmt.py
4
100.0
 /home/travis/virtualenv/python2.7.9/lib/python2.7/site-packages/rhea/vendor/xilinx/device_clock_mgmt.py
4
100.0
 /home/travis/virtualenv/python3.5.2/lib/python3.5/site-packages/rhea/vendor/xilinx/device_clock_mgmt.py
Jobs
ID Job ID Ran Files Coverage
1 439.1 0
70.39
 Travis Job 439.1
2 439.2 0
70.39
 Travis Job 439.2
3 439.3 0
70.42
 Travis Job 439.3
Source Files on build 439
Detailed source file information is not available for this build.