ben-manes / caffeine / #4880
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coverage: 99.948%. Remained the same
#4880

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ben-manes 
Use stronger memory order to avoid publication races (fixes #1820)

TSAN detected a theoretical race for a weak valued cache during a #put
call. This can happen on a weak memory model like aarch64 if it also
aggressively reorders. Tracing with Charles Munger (Google), we decided
that the key and value should use acquire semantics and opaque
elsewhere to document the intentions. However this was based on logical
reasoning of our understandings of the memory models, as we could not
reproduce the results to determine if it was a true or false positive.
The TSAN issue pointed to the WeakReference constructor accepting the
key reference as a plain field and being read as one, which should be
benign race as either the user's or a sentinel value.

On a 14-core M3 Max, under heavy load the existing test
Issue568Test#intermittentNull() fails due to incorrectly observing a
null value. The additional multi-threaded test cases incur enough load
to trigger this on this machine. The CircleCI arm64 instance does not
aggressive recorder enough or offer enough concurrency to expose this
race. This is different from the TSAN issue, but highlights the same
fundamental flaw.

Release semantics only apply to the field itself and does not provide
a strong enough happens-before edge for the newly constructed object
for its publication to be complete. A volatile fence is required in
this case since the fields are non-final.

7730 of 7734 relevant lines covered (99.95%)

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ID Job ID Ran Files Coverage
1 #4880.1 78
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Source Files on build #4880