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Qiskit / qiskit / 13730247126
88%

Build:
DEFAULT BRANCH: main
Ran 07 Mar 2025 10:34PM UTC
Jobs 1
Files 788
Run time 6min
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07 Mar 2025 09:31PM UTC coverage: 88.137% (-0.09%) from 88.23%
13730247126

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Move `Bit` and `Register` to live in Rust space (#13860)

* Initial: Add `Bit` and `Register` initial structs

Co-authored-by: Jake Lishman <jake.lishman@ibm.com>

* Add: `AncillaQubit` and `Clbit` python counterparts

* Add: `QuantumRegister` and `ClassicalRegister` python counterparts.
- Use `macro_rules!` to create `Bit` and `Registers`.

* Add: `AncillaRegister`

* Fix: Display methods
- Add `new_owned` method for `BitInfo`.

* Fix: Rebalance API to allow for superclasses
- Rebalance currently available api to allow for superclasses `Bit` and `Register` to also live in Rust.
- Remove: `ShareableBit` triat and structs that implement it. Replace them with new structs.

* Fix: Temporarily replace python instance, prepare for deletion.
- Add prefix class attribute for python `Register` instances.

* Fix: More rebalancing of the API.
- Add `BitExtraInfo` as a soft identifier for `BitInfo`, can be null to identify a `Bit`.
- Add `RegisterInfo::get` method to retrieve the information of a `Bit`.
- Have the rust registers own their counters instead of having them be Python exclusive.
- Make subclassing of `Regster` and `Bit` a bit more effective by helping the subclasses inherit most methods.

* Remove: `__getstate__`, `__setstate__` methods from `PyBit`.

* Fix: Intitial move to using rust native bits in `CircuitData` and `DAGCircuit`.
- Modify `BitData` to accept an extra generic value specifying a "sharable" object type that can also be turned into a `PyObject` to allow for compatibility with `Var`.
- Rename `BitAsKey` to `VarAsKey` as it is currently only used for `Var` instances.
- Modify methods in `CommutationChecker` and `GateDirection` passes to use the newer methods.
- Other tweaks and fixes.

* Fix: Implement `FromPyObject<'_>` for `SharableQubit` and `SharableClbit`.
- Remove imports of `QUBIT` and `CLBIT` from `DAGCircuit` and `CircuitData`.

* Fix: Discard cache when bits are added to `BitData`
- Discarded old equality and hashing methods fo... (continued)

1631 of 1909 new or added lines in 81 files covered. (85.44%)

27 existing lines in 5 files now uncovered.

72642 of 82419 relevant lines covered (88.14%)

497302.37 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
2
94.21
-2.31% qiskit/circuit/library/blueprintcircuit.py
3
94.55
crates/circuit/src/bit_locator.rs
5
93.63
0.17% qiskit/circuit/quantumcircuit.py
7
0.0
0.0% crates/circuit/src/dot_utils.rs
8
92.59
-2.02% crates/circuit/src/bit_data.rs
8
94.17
-1.33% qiskit/visualization/circuit/_utils.py
40
73.15
crates/circuit/src/register_data.rs
45
91.8
-1.84% crates/circuit/src/circuit_data.rs
73
86.63
crates/circuit/src/bit.rs
87
86.02
-0.26% crates/circuit/src/dag_circuit.rs

Uncovered Existing Lines

Lines Coverage ∆ File
1
92.59
-2.02% crates/circuit/src/bit_data.rs
1
94.21
-2.31% qiskit/circuit/library/blueprintcircuit.py
3
93.23
0.75% crates/qasm2/src/lex.rs
10
86.02
-0.26% crates/circuit/src/dag_circuit.rs
12
97.15
-0.46% crates/qasm2/src/parse.rs
Jobs
ID Job ID Ran Files Coverage
1 13730247126.1 07 Mar 2025 10:34PM UTC 788
88.14
GitHub Action Run
Source Files on build 13730247126
  • Tree
  • List 788
  • Changed 82
  • Source Changed 80
  • Coverage Changed 51
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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