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Qiskit / qiskit / 13698067235
88%

Build:
DEFAULT BRANCH: main
Ran 06 Mar 2025 12:15PM UTC
Jobs 1
Files 789
Run time 238min
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06 Mar 2025 11:12AM UTC coverage: 88.178% (-0.01%) from 88.189%
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The parameter ``idle_wires`` default flipped to False in all circuit drawers (#13865)

* The parameter ``idle_wires`` default flipped to False in all circuit drawers

* reno

* readjust tests

* test.python.visualization.test_circuit_text_drawer

* adjust visual tests

* bug in the tests

* adjust test

* black

* testing

* adjust tests

* revert test changes

* new reno

* fix layout-related plots

there's some bloch sphere plot failure which likely shouldn't be related to this, let's see if it persists

* top-level handling of "auto"

handle "auto" at the circuit_drawer level and subsequently use on booleans in internal logic

* Fix idle_wires None case

Co-authored-by: Jake Lishman <jake@binhbar.com>

---------

Co-authored-by: Julien Gacon <jules.gacon@googlemail.com>
Co-authored-by: Julien Gacon <gaconju@gmail.com>
Co-authored-by: Jake Lishman <jake@binhbar.com>

4 of 5 new or added lines in 1 file covered. (80.0%)

19 existing lines in 4 files now uncovered.

71841 of 81473 relevant lines covered (88.18%)

487917.15 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
73.29
0.05% qiskit/visualization/circuit/circuit_visualization.py

Uncovered Existing Lines

Lines Coverage ∆ File
1
94.29
-0.1% crates/accelerate/src/unitary_synthesis.rs
1
94.23
-0.23% crates/qasm2/src/expr.rs
5
92.48
-0.25% crates/qasm2/src/lex.rs
12
97.15
-0.46% crates/qasm2/src/parse.rs
Jobs
ID Job ID Ran Files Coverage
1 13698067235.1 06 Mar 2025 12:15PM UTC 789
88.18
GitHub Action Run
Source Files on build 13698067235
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  • List 789
  • Changed 7
  • Source Changed 3
  • Coverage Changed 7
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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