cfelton / rhea / 396
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DEFAULT BRANCH: master
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Jobs 3
Files 516
Run time 8min
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Merge pull request #31 from NickShaffner/master

Added addtional port mappings to Digilent Anvyl board

13961 of 19695 relevant lines covered (70.89%)

0.71 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
1
100.0
 /home/travis/virtualenv/python3.5.2/lib/python3.5/site-packages/rhea/build/boards/xilinx/_anvyl.py
1
100.0
 /home/travis/virtualenv/python3.4.2/lib/python3.4/site-packages/rhea/build/boards/xilinx/_anvyl.py
1
100.0
 /home/travis/virtualenv/python2.7.9/lib/python2.7/site-packages/rhea/build/boards/xilinx/_anvyl.py
Jobs
ID Job ID Ran Files Coverage
1 396.1 0
70.88
 Travis Job 396.1
2 396.2 0
70.88
 Travis Job 396.2
3 396.3 0
70.91
 Travis Job 396.3
Source Files on build 396
Detailed source file information is not available for this build.