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Warning: This build has drifted.
The coverage report for this pull request build may be inaccurate because its base commit is no longer the HEAD of its target branch.
This means it includes changes from outside the original pull request, including, potentially, unrelated coverage changes.

    • Learn more: For more information on this, see Tracking coverage changes for pull request builds.
    • Fix now: For a quick fix, rebase this PR at GitHub. Your next report should be accurate.
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IntelPython / dpctl / 10146760422
88%
master: 86%

Build:
Build:
LAST BUILD BRANCH: disallow_conv_to_scalar_ndim
DEFAULT BRANCH: master
Ran 29 Jul 2024 03:39PM UTC
Jobs 1
Files 79
Run time 1min
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29 Jul 2024 02:59PM UTC coverage: 87.609%. Remained the same
10146760422

Pull #1753

github

web-flow
Merge 69aa1edcf into ef9ebc8f4
Pull Request #1753: Release GIL around blocking operations in libtensor

3328 of 3846 branches covered (86.53%)

Branch coverage included in aggregate %.

5 of 6 new or added lines in 1 file covered. (83.33%)

11265 of 12811 relevant lines covered (87.93%)

7368.25 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
95.4
-0.8% dpctl/utils/_order_manager.py
Jobs
ID Job ID Ran Files Coverage
1 10146760422.1 29 Jul 2024 03:40PM UTC 103
79.27
GitHub Action Run
Source Files on build 10146760422
  • Tree
  • List 79
  • Changed 23
  • Source Changed 0
  • Coverage Changed 16
Coverage ∆ File Lines Relevant Covered Missed Hits/Line Branch Hits Branch Misses
  • Back to Repo
  • Pull Request #1753
  • PR Base - master (#10136955542)
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