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OFS / opae-sdk / 7025280281
64%

Build:
DEFAULT BRANCH: master
Ran 28 Nov 2023 10:37PM UTC
Jobs 1
Files 139
Run time 10s
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28 Nov 2023 10:24PM UTC coverage: 67.621% (-0.06%) from 67.679%
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Feature:add loop count command line input to CXL host exerciser (#3051)

- add loop count  command line input and set read /write config
  - set FPGA / host  read and write cache miss opcode to  RD_LINE_I /WR_LINE_I

Signed-off-by: anandaravuri <ananda.ravuri@intel.com>

0 of 25 new or added lines in 2 files covered. (0.0%)

4 existing lines in 1 file now uncovered.

15755 of 23299 relevant lines covered (67.62%)

9407.12 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
2
0.0
0.0% samples/cxl_host_exerciser/he_cache_test.h
23
0.0
0.0% samples/cxl_host_exerciser/cxl_he_cache_cmd.h

Uncovered Existing Lines

Lines Coverage ∆ File
4
0.0
0.0% samples/cxl_host_exerciser/cxl_he_cache_cmd.h
Jobs
ID Job ID Ran Files Coverage
1 7025280281.1 28 Nov 2023 10:37PM UTC 139
67.62
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Source Files on build 7025280281
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  • Changed 7
  • Source Changed 0
  • Coverage Changed 3
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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