SRI-CSL / yices2 / 6916468634
65%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 471
Run time 56s
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coverage: 65.146% (+0.002%) from 65.144%
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Merge pull request #473 from SRI-CSL/fix-compilation-warnings

fix compilation warnings and enable the -Werror flag in CI

8 of 11 new or added lines in 4 files covered. (72.73%)

3 existing lines in 3 files now uncovered.

79299 of 121725 relevant lines covered (65.15%)

1507466.29 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
0.0
 0.0% src/solvers/cdcl/new_sat_solver.c
2
64.36
 0.0% src/terms/power_products.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
66.14
 1.03% src/mcsat/bool/clause_db.c
1
61.65
 0.46% src/mcsat/bv/bv_explainer.c
1
77.61
 0.06% src/mcsat/solver.c
Jobs
ID Job ID Ran Files Coverage
1 6916468634.1 1615
65.75
 GitHub Action Run
Source Files on build 6916468634