Qiskit / qiskit-terra / 5543757430

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Relax wire_order restrictions in circuit visualization (#9893)

* first attempt

* fixing

* other drawers

* revert test/ipynb/mpl_tester.ipynb

* corner case

* latex test

* reno

* readjust based on https://github.com/Qiskit/qiskit-terra/pull/9893#issuecomment-1494383052

* default complete_wire_order

* test adjustmet

* bug in length

* readjust tests

* ref

* remove old ref

* new ref

* revert https://github.com/Qiskit/qiskit-terra/pull/9893/files#r1259615851

* remove tests because they do not cover the extended code

* reno fix

11 of 11 new or added lines in 1 file covered. (100.0%)

71695 of 83383 relevant lines covered (85.98%)

31635.15 hits per line