#195

Committed 16 Apr 2023 01:39PM UTC coverage: 62.515% (+0.08%) from 62.437%

Build # #195

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travis-ci

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web-flow

Commit Message

Merge pull request #176 from AmeyaVS/fix/primitive-verilog-code

Initial Version to fix Verilog Primitive Structural Code(Fixes #173)

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92.56

/src/svConvertor/gateParser.cpp

#include <hdlConvertor/svConvertor/gateParser.h>
#include <hdlConvertor/svConvertor/exprParser.h>
#include <hdlConvertor/svConvertor/utils.h>
#include <hdlConvertor/hdlAst/hdlStmAssign.h>
#include <hdlConvertor/createObject.h>
#include <hdlConvertor/notImplementedLogger.h>
#include <hdlConvertor/hdlAst/hdlCompInst.h>

#include <cassert>


namespace hdlConvertor {
namespace sv {

using namespace std;
using namespace hdlConvertor::hdlAst;


std::unique_ptr<iHdlExprItem> VerGateParser::visitEnable_terminal(
                sv2017Parser::Enable_terminalContext *ctx) {
        // enable_terminal: expression;
        return VerExprParser(this).visitExpression(ctx->expression());
}
std::unique_ptr<iHdlExprItem> VerGateParser::visitInout_terminal(
                sv2017Parser::Inout_terminalContext *ctx) {
        // inout_terminal: net_lvalue;
        return VerExprParser(this).visitNet_lvalue(ctx->net_lvalue());
}

std::unique_ptr<iHdlExprItem> VerGateParser::visitInput_terminal(
                sv2017Parser::Input_terminalContext *ctx) {
        // input_terminal: expression;
        return VerExprParser(this).visitExpression(ctx->expression());
}

std::unique_ptr<iHdlExprItem> VerGateParser::visitOutput_terminal(
                sv2017Parser::Output_terminalContext *ctx) {
        // output_terminal: net_lvalue;
        return VerExprParser(this).visitNet_lvalue(ctx->net_lvalue());
}

HdlOpType VerGateParser::visitN_output_gatetype(
                sv2017Parser::N_output_gatetypeContext *ctx) {
        // n_output_gatetype:
        //  KW_BUF
        //   | KW_NOT
        // ;
        if (ctx->KW_BUF()) {
                return HdlOpType::ASSIGN;
        } else {
                assert(ctx->KW_NOT());
                return HdlOpType::NEG;
        }
}

HdlOpType VerGateParser::visitN_input_gatetype(
                sv2017Parser::N_input_gatetypeContext *ctx) {
        // n_input_gatetype:
        // KW_AND
        // | KW_NAND
        // | KW_OR
        // | KW_NOR
        // | KW_XOR
        // | KW_XNOR
        // ;
        if(ctx->KW_AND()) {
                return HdlOpType::AND;
        }
        if (ctx->KW_NAND()) {
                return HdlOpType::NAND;
        }
        if (ctx->KW_OR()) {
                return HdlOpType::OR;
        }
        if (ctx->KW_NOR()) {
                return HdlOpType::NOR;
        }
        if (ctx->KW_XOR()) {
                return HdlOpType::XOR;
        }
        assert(ctx->KW_XNOR());
        {
                return HdlOpType::XNOR;
        }
}

std::pair<std::unique_ptr<iHdlExprItem>, std::unique_ptr<iHdlExprItem>> VerGateParser::visitN_output_gate_instance(
                sv2017Parser::N_output_gate_instanceContext *ctx) {
        // n_output_gate_instance:
        //  ( name_of_instance )? LPAREN output_terminal ( COMMA output_terminal )* COMMA input_terminal
        //       RPAREN;
        auto noi = ctx->name_of_instance();
        if (noi) {
                // name_of_instance: identifier ( unpacked_dimension )*;
                // auto name = VerExprParser::visitIdentifier(noi->identifier());
                NotImplementedLogger::print(
                                "VerGateParser.visitN_output_gate_instance name_of_instance",
                                ctx);
        }
        vector<unique_ptr<iHdlExprItem>> outputs;
        for (auto _ot : ctx->output_terminal()) {
                outputs.push_back(visitOutput_terminal(_ot));
        }
        auto _it = ctx->input_terminal();
        auto it = visitInput_terminal(_it);
        if (outputs.size() > 1) {
                auto o = reduce(outputs, HdlOpType::CONCAT);
                return {move(o), move(it)};
        } else {
                return {move(outputs[0]), move(it)};
        }
}

std::vector<std::unique_ptr<iHdlExprItem>> VerGateParser::visitN_input_gate_instance(
                sv2017Parser::N_input_gate_instanceContext *ctx) {
        // n_input_gate_instance:
        // ( name_of_instance )? LPAREN output_terminal ( COMMA input_terminal )+ RPAREN;
        auto noi = ctx->name_of_instance();
        if (noi) {
                // name_of_instance: identifier ( unpacked_dimension )*;
                // auto name = VerExprParser::visitIdentifier(noi->identifier());
                NotImplementedLogger::print(
                                "VerGateParser.visitN_input_gate_instance name_of_instance",
                                ctx);
        }
        auto _ot = ctx->output_terminal();
        vector<unique_ptr<iHdlExprItem>> terminals;
        terminals.emplace_back(visitOutput_terminal(_ot));
        for(auto _it : ctx->input_terminal()) {
                terminals.emplace_back(visitInput_terminal(_it));
        }
        return terminals;
}

void VerGateParser::visitGate_instantiation(
                sv2017Parser::Gate_instantiationContext *ctx,
                std::vector<std::unique_ptr<hdlAst::iHdlObj>> &res) {
        // gate_instantiation:
        //  ( ( KW_PULLDOWN ( pulldown_strength )?
        //       | KW_PULLUP ( pullup_strength )?
        //       ) pull_gate_instance ( COMMA pull_gate_instance )*
        //   | ( cmos_switchtype | mos_switchtype) ( delay3 )? enable_gate_or_mos_switch_or_cmos_switch_instance ( COMMA enable_gate_or_mos_switch_or_cmos_switch_instance )*
        //   | enable_gatetype ( drive_strength )? ( delay3 )? enable_gate_or_mos_switch_or_cmos_switch_instance ( COMMA enable_gate_or_mos_switch_or_cmos_switch_instance )*
        //   | n_input_gatetype ( drive_strength )? ( delay2 )? n_input_gate_instance ( COMMA  n_input_gate_instance )*
        //   | n_output_gatetype ( drive_strength )? ( delay2 )? n_output_gate_instance ( COMMA n_output_gate_instance )*
        //   | pass_en_switchtype ( delay2 )? pass_enable_switch_instance ( COMMA pass_enable_switch_instance )*
        //   | pass_switchtype pass_switch_instance ( COMMA pass_switch_instance )*
        //   ) SEMI
        // ;

        auto _ot = ctx->n_output_gatetype();
        if (_ot) {
                auto ot = visitN_output_gatetype(_ot);
                auto ds = ctx->drive_strength();
                if (ds) {
                        NotImplementedLogger::print(
                                        "VerGateParser.visitGate_instantiation drive_strength",
                                        ctx);
                }
                auto d2 = ctx->delay2();
                if (d2) {
                        NotImplementedLogger::print(
                                        "VerGateParser.visitGate_instantiation delay2", ctx);
                }
                for (auto ogi : ctx->n_output_gate_instance()) {
                        unique_ptr<HdlStmAssign> a;
                        auto output_input = visitN_output_gate_instance(ogi);
                        if (ot == HdlOpType::ASSIGN) {
                                a = create_object<HdlStmAssign>(ogi, move(output_input.first),
                                                move(output_input.second), false);
                        } else if (ot == HdlOpType::NEG) {
                                auto i = create_object<HdlOp>(ogi, HdlOpType::NEG,
                                                move(output_input.second));
                                a = create_object<HdlStmAssign>(ogi, move(output_input.first),
                                                move(i), false);
                        }
                        res.push_back(move(a));
                }
        } else if (auto _ot2 = ctx->n_input_gatetype()) {
                auto ot = visitN_input_gatetype(_ot2);
                auto ds = ctx->drive_strength();
                if (ds) {
                        NotImplementedLogger::print(
                                        "VerGateParser.visitGate_instantiation drive_strength",
                                        ctx);
                }
                auto d2 = ctx->delay2();
                if (d2) {
                        NotImplementedLogger::print(
                                        "VerGateParser.visitGate_instantiation delay2", ctx);
                }
                for (auto ogi : ctx->n_input_gate_instance()) {
                        unique_ptr<HdlCompInst> a;
                        auto output_input = visitN_input_gate_instance(ogi);
                        //
                        // n_input_gatetype:
                        // KW_AND
                        // | KW_NAND
                        // | KW_OR
                        // | KW_NOR
                        // | KW_XOR
                        // | KW_XNOR
                        // ;
                        auto noi = ogi->name_of_instance();
                        auto name = (noi)?VerExprParser::visitIdentifier(noi->identifier()): make_unique<HdlValueId>(" ");
                        std::unique_ptr<HdlValueId> gt;
                        switch(ot) {
                                case HdlOpType::AND:
                                        gt = create_object<HdlValueId>(ogi, "and");
                                break;
                                case HdlOpType::NAND:
                                        gt = create_object<HdlValueId>(ogi, "nand");
                                break;
                                case HdlOpType::OR:
                                        gt = create_object<HdlValueId>(ogi, "or");
                                break;
                                case HdlOpType::NOR:
                                        gt = create_object<HdlValueId>(ogi, "nor");
                                break;
                                case HdlOpType::XOR:
                                        gt = create_object<HdlValueId>(ogi, "xor");
                                break;
                                case HdlOpType::XNOR:
                                        gt = create_object<HdlValueId>(ogi, "xnor");
                                break;
                                default:
                                        // Should not reach here!
                                        assert(false);
                                break;
                        }
                        if (gt) {
                                a = create_object<HdlCompInst>(ogi, move(name), move(gt));
                                a->portMap = move(output_input);
                        }
                        if(a)
                                res.push_back(move(a));
                }
        } else {
                NotImplementedLogger::print("VerGateParser.visitGate_instantiation",
                                ctx);
        }
}

}
}

1	#include <hdlConvertor/svConvertor/gateParser.h>
2	#include <hdlConvertor/svConvertor/exprParser.h>
3	#include <hdlConvertor/svConvertor/utils.h>
4	#include <hdlConvertor/hdlAst/hdlStmAssign.h>
5	#include <hdlConvertor/createObject.h>
6	#include <hdlConvertor/notImplementedLogger.h>
7	#include <hdlConvertor/hdlAst/hdlCompInst.h>
8
9	#include <cassert>
10
11
12	namespace hdlConvertor {
13	namespace sv {
14
15	using namespace std;
16	using namespace hdlConvertor::hdlAst;
17
18
19	std::unique_ptr<iHdlExprItem> VerGateParser::visitEnable_terminal(	×
20	sv2017Parser::Enable_terminalContext *ctx) {
21	// enable_terminal: expression;
22	return VerExprParser(this).visitExpression(ctx->expression());	×
23	}
24	std::unique_ptr<iHdlExprItem> VerGateParser::visitInout_terminal(	×
25	sv2017Parser::Inout_terminalContext *ctx) {
26	// inout_terminal: net_lvalue;
27	return VerExprParser(this).visitNet_lvalue(ctx->net_lvalue());	×
28	}
29
30	std::unique_ptr<iHdlExprItem> VerGateParser::visitInput_terminal(	2,257✔
31	sv2017Parser::Input_terminalContext *ctx) {
32	// input_terminal: expression;
33	return VerExprParser(this).visitExpression(ctx->expression());	4,514✔
34	}
35
36	std::unique_ptr<iHdlExprItem> VerGateParser::visitOutput_terminal(	2,022✔
37	sv2017Parser::Output_terminalContext *ctx) {
38	// output_terminal: net_lvalue;
39	return VerExprParser(this).visitNet_lvalue(ctx->net_lvalue());	4,044✔
40	}
41
42	HdlOpType VerGateParser::visitN_output_gatetype(	1,817✔
43	sv2017Parser::N_output_gatetypeContext *ctx) {
44	// n_output_gatetype:
45	// KW_BUF
46	// \| KW_NOT
47	// ;
48	if (ctx->KW_BUF()) {	1,817✔
49	return HdlOpType::ASSIGN;	1,755✔
50	} else {
51	assert(ctx->KW_NOT());	62✔
52	return HdlOpType::NEG;	62✔
53	}
54	}
55
56	HdlOpType VerGateParser::visitN_input_gatetype(	177✔
57	sv2017Parser::N_input_gatetypeContext *ctx) {
58	// n_input_gatetype:
59	// KW_AND
60	// \| KW_NAND
61	// \| KW_OR
62	// \| KW_NOR
63	// \| KW_XOR
64	// \| KW_XNOR
65	// ;
66	if(ctx->KW_AND()) {	177✔
67	return HdlOpType::AND;	49✔
68	}
69	if (ctx->KW_NAND()) {	128✔
70	return HdlOpType::NAND;	34✔
71	}
72	if (ctx->KW_OR()) {	94✔
73	return HdlOpType::OR;	34✔
74	}
75	if (ctx->KW_NOR()) {	60✔
76	return HdlOpType::NOR;	5✔
77	}
78	if (ctx->KW_XOR()) {	55✔
79	return HdlOpType::XOR;	49✔
80	}
81	assert(ctx->KW_XNOR());	6✔
82	{
83	return HdlOpType::XNOR;	6✔
84	}
85	}
86
87	std::pair<std::unique_ptr<iHdlExprItem>, std::unique_ptr<iHdlExprItem>> VerGateParser::visitN_output_gate_instance(	1,819✔
88	sv2017Parser::N_output_gate_instanceContext *ctx) {
89	// n_output_gate_instance:
90	// ( name_of_instance )? LPAREN output_terminal ( COMMA output_terminal )* COMMA input_terminal
91	// RPAREN;
92	auto noi = ctx->name_of_instance();	1,819✔
93	if (noi) {	1,819✔
94	// name_of_instance: identifier ( unpacked_dimension )*;
95	// auto name = VerExprParser::visitIdentifier(noi->identifier());
96	NotImplementedLogger::print(	131✔
97	"VerGateParser.visitN_output_gate_instance name_of_instance",
98	ctx);
99	}
100	vector<unique_ptr<iHdlExprItem>> outputs;	1,819✔
101	for (auto _ot : ctx->output_terminal()) {	3,645✔
102	outputs.push_back(visitOutput_terminal(_ot));	1,826✔
103	}	1,819✔
104	auto _it = ctx->input_terminal();	1,819✔
105	auto it = visitInput_terminal(_it);	1,819✔
106	if (outputs.size() > 1) {	1,819✔
107	auto o = reduce(outputs, HdlOpType::CONCAT);	4✔
108	return {move(o), move(it)};	4✔
109	} else {	4✔
110	return {move(outputs[0]), move(it)};	1,815✔
111	}
112	}	1,819✔
113
114	std::vector<std::unique_ptr<iHdlExprItem>> VerGateParser::visitN_input_gate_instance(	196✔
115	sv2017Parser::N_input_gate_instanceContext *ctx) {
116	// n_input_gate_instance:
117	// ( name_of_instance )? LPAREN output_terminal ( COMMA input_terminal )+ RPAREN;
118	auto noi = ctx->name_of_instance();	196✔
119	if (noi) {	196✔
120	// name_of_instance: identifier ( unpacked_dimension )*;
121	// auto name = VerExprParser::visitIdentifier(noi->identifier());
122	NotImplementedLogger::print(	132✔
123	"VerGateParser.visitN_input_gate_instance name_of_instance",
124	ctx);
125	}
126	auto _ot = ctx->output_terminal();	196✔
127	vector<unique_ptr<iHdlExprItem>> terminals;	196✔
128	terminals.emplace_back(visitOutput_terminal(_ot));	196✔
129	for(auto _it : ctx->input_terminal()) {	634✔
130	terminals.emplace_back(visitInput_terminal(_it));	438✔
131	}	196✔
132	return terminals;	196✔
133	}	×
134
135	void VerGateParser::visitGate_instantiation(	2,755✔
136	sv2017Parser::Gate_instantiationContext *ctx,
137	std::vector<std::unique_ptr<hdlAst::iHdlObj>> &res) {
138	// gate_instantiation:
139	// ( ( KW_PULLDOWN ( pulldown_strength )?
140	// \| KW_PULLUP ( pullup_strength )?
141	// ) pull_gate_instance ( COMMA pull_gate_instance )*
142	// \| ( cmos_switchtype \| mos_switchtype) ( delay3 )? enable_gate_or_mos_switch_or_cmos_switch_instance ( COMMA enable_gate_or_mos_switch_or_cmos_switch_instance )*
143	// \| enable_gatetype ( drive_strength )? ( delay3 )? enable_gate_or_mos_switch_or_cmos_switch_instance ( COMMA enable_gate_or_mos_switch_or_cmos_switch_instance )*
144	// \| n_input_gatetype ( drive_strength )? ( delay2 )? n_input_gate_instance ( COMMA n_input_gate_instance )*
145	// \| n_output_gatetype ( drive_strength )? ( delay2 )? n_output_gate_instance ( COMMA n_output_gate_instance )*
146	// \| pass_en_switchtype ( delay2 )? pass_enable_switch_instance ( COMMA pass_enable_switch_instance )*
147	// \| pass_switchtype pass_switch_instance ( COMMA pass_switch_instance )*
148	// ) SEMI
149	// ;
150
151	auto _ot = ctx->n_output_gatetype();	2,755✔
152	if (_ot) {	2,755✔
153	auto ot = visitN_output_gatetype(_ot);	1,817✔
154	auto ds = ctx->drive_strength();	1,817✔
155	if (ds) {	1,817✔
156	NotImplementedLogger::print(	10✔
157	"VerGateParser.visitGate_instantiation drive_strength",
158	ctx);
159	}
160	auto d2 = ctx->delay2();	1,817✔
161	if (d2) {	1,817✔
162	NotImplementedLogger::print(	52✔
163	"VerGateParser.visitGate_instantiation delay2", ctx);
164	}
165	for (auto ogi : ctx->n_output_gate_instance()) {	3,636✔
166	unique_ptr<HdlStmAssign> a;	1,819✔
167	auto output_input = visitN_output_gate_instance(ogi);	1,819✔
168	if (ot == HdlOpType::ASSIGN) {	1,819✔
169	a = create_object<HdlStmAssign>(ogi, move(output_input.first),	3,514✔
170	move(output_input.second), false);	5,271✔
171	} else if (ot == HdlOpType::NEG) {	62✔
172	auto i = create_object<HdlOp>(ogi, HdlOpType::NEG,	×
173	move(output_input.second));	62✔
174	a = create_object<HdlStmAssign>(ogi, move(output_input.first),	124✔
175	move(i), false);	124✔
176	}	62✔
177	res.push_back(move(a));	1,819✔
178	}	3,636✔
179	} else if (auto _ot2 = ctx->n_input_gatetype()) {	938✔
180	auto ot = visitN_input_gatetype(_ot2);	177✔
181	auto ds = ctx->drive_strength();	177✔
182	if (ds) {	177✔
183	NotImplementedLogger::print(	×
184	"VerGateParser.visitGate_instantiation drive_strength",
185	ctx);
186	}
187	auto d2 = ctx->delay2();	177✔
188	if (d2) {	177✔
189	NotImplementedLogger::print(	20✔
190	"VerGateParser.visitGate_instantiation delay2", ctx);
191	}
192	for (auto ogi : ctx->n_input_gate_instance()) {	373✔
193	unique_ptr<HdlCompInst> a;	196✔
194	auto output_input = visitN_input_gate_instance(ogi);	196✔
195	//
196	// n_input_gatetype:
197	// KW_AND
198	// \| KW_NAND
199	// \| KW_OR
200	// \| KW_NOR
201	// \| KW_XOR
202	// \| KW_XNOR
203	// ;
204	auto noi = ogi->name_of_instance();	196✔
205	auto name = (noi)?VerExprParser::visitIdentifier(noi->identifier()): make_unique<HdlValueId>(" ");	196✔
206	std::unique_ptr<HdlValueId> gt;	196✔
207	switch(ot) {	196✔
208	case HdlOpType::AND:	54✔
209	gt = create_object<HdlValueId>(ogi, "and");	54✔
210	break;	54✔
211	case HdlOpType::NAND:	48✔
212	gt = create_object<HdlValueId>(ogi, "nand");	48✔
213	break;	48✔
214	case HdlOpType::OR:	34✔
215	gt = create_object<HdlValueId>(ogi, "or");	34✔
216	break;	34✔
217	case HdlOpType::NOR:	5✔
218	gt = create_object<HdlValueId>(ogi, "nor");	5✔
219	break;	5✔
220	case HdlOpType::XOR:	49✔
221	gt = create_object<HdlValueId>(ogi, "xor");	49✔
222	break;	49✔
223	case HdlOpType::XNOR:	6✔
224	gt = create_object<HdlValueId>(ogi, "xnor");	6✔
225	break;	6✔
226	default:	×
227	// Should not reach here!
228	assert(false);	×
229	break;
230	}
231	if (gt) {	196✔
232	a = create_object<HdlCompInst>(ogi, move(name), move(gt));	196✔
233	a->portMap = move(output_input);	196✔
234	}
235	if(a)	196✔
236	res.push_back(move(a));	196✔
237	}	373✔
238	} else {
239	NotImplementedLogger::print("VerGateParser.visitGate_instantiation",	761✔
240	ctx);
241	}
242	}	2,755✔
243
244	}
245	}

Nic30 / hdlConvertor / #195

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