Nic30 / hdlConvertor / #189
63%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 117
Run time 7s
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coverage: 62.437% (-1.3%) from 63.783%
#189

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34106 of 54625 relevant lines covered (62.44%)

15694.86 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
41
63.51
 -2.03% src/verilogPreproc/verilogPreprocParser/verilogPreprocParser.cpp
238
62.57
 -1.91% src/vhdlConvertor/vhdlParser/vhdlParser.cpp
459
56.33
 -1.48% src/svConvertor/sv2017Parser/sv2017Parser.cpp
Jobs
ID Job ID Ran Files Coverage
1 #189.1 117
62.44
Source Files on build #189