lsils / mockturtle / ad557082ea085a23859c2cbae776f4e19b1cf018
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Jobs 1
Files 93
Run time 14s
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ad557082ea085a23859c2cbae776f4e19b1cf018

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Update changes in lorina's Verilog parser. (#325)

7569 of 9515 relevant lines covered (79.55%)

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ID Job ID Ran Files Coverage
1 ad557082ea085a23859c2cbae776f4e19b1cf018.1 0
79.55
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Source Files on build ad557082ea085a23859c2cbae776f4e19b1cf018
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