Bo-Yuan-Huang / ILAng / 437
86%

DEFAULT BRANCH: master
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Jobs 1
Files 81
Run time 4s
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Merge pull request #41 from zhanghongce/master

Verilog Target Gen

5942 of 7430 relevant lines covered (79.97%)

37052.08 hits per line

Jobs
ID Job ID Ran Files Coverage
1 437.1 0
79.97
 Travis Job 437.1
Source Files on build 437
Detailed source file information is not available for this build.