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cmu-db / terrier / 314
95%

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DEFAULT BRANCH: master
Ran 09 Aug 2018 09:42PM UTC
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Files 0
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Replace our spin_latch implementation with TBB's.

 Skylake and newer processors increase the PAUSE latency by an order of magnitude, so efficient spinning requires more work. Intel handles this for us in their spin_mutex with tbb::internal::atomic_backoff. (#87)
Jobs
ID Job ID Ran Files Coverage
7 314.7 (NAME="Docker[Coverage/Dockerfile]" CMAKE_BUILD_TYPE=debug TERRIER_USE_ASAN=Off DOCKER=true) 09 Aug 2018 09:42PM UTC 0
42.7
Travis Job 314.7
Source Files on build 314
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