SiLab-Bonn / basil / 780
32%
master: 32%

LAST BUILD BRANCH: new_bus_interface
DEFAULT BRANCH: master
Ran
Jobs 1
Files 66
Run time 3s
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780

Pull #79

travis-ci

web-flow 
REV: not needed logging related changes
Pull Request #79: ENH: use module level logging

71 of 71 new or added lines in 19 files covered. (100.0%)

1347 of 3732 relevant lines covered (36.09%)

0.36 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
42.47
 0.31% basil/HL/FEI4AdapterCard.py
1
84.62
 0.62% basil/HL/bram_fifo.py
1
88.0
 0.5% basil/TL/Visa.py
2
0.0
 0.0% basil/HL/FEI4QuadModuleAdapterCard.py
2
92.05
 0.05% basil/HL/RegisterHardwareLayer.py
2
0.0
 0.0% basil/TL/Serial.py
2
0.0
 0.0% basil/TL/SiTcp.py
2
0.0
 0.0% basil/TL/SiUsb3.py
3
0.0
 0.0% basil/HL/MIO_PLL.py
3
0.0
 0.0% basil/HL/NTCRegister.py
4
0.0
 0.0% basil/HL/GPAC.py
4
73.81
 0.64% basil/HL/sram_fifo.py
5
0.0
 0.0% basil/HL/iseg_shq.py
6
0.0
 0.0% basil/TL/SiUsb.py
15
0.0
 0.0% basil/TL/SiUart.py

Uncovered Existing Lines

Lines Coverage ∆ File
1
0.0
 0.0% basil/HL/GPAC.py
1
0.0
 0.0% basil/HL/MIO_PLL.py
1
0.0
 0.0% basil/HL/iseg_shq.py
1
0.0
 0.0% basil/HL/sitcp_fifo.py
1
0.0
 0.0% basil/TL/SiUsb.py
1
0.0
 0.0% basil/TL/SiUsb3.py
1
88.0
 0.5% basil/TL/Visa.py
1
0.0
 0.0% basil/TL/SiTcp.py
2
92.05
 0.05% basil/HL/RegisterHardwareLayer.py
3
73.81
 0.64% basil/HL/sram_fifo.py
6
0.0
 0.0% basil/TL/SiUart.py
Jobs
ID Job ID Ran Files Coverage
1 780.1 66
36.09
 Travis Job 780.1
Source Files on build 780
Coverage ∆ File Lines Relevant Covered Missed Hits/Line