Nic30 / hdlConvertor / 591

Builds Branch Commit Type Ran Committer Via Coverage
591 sv2017 rm verbose from coveralls-lcov, outputs is beyolond the travis limit push Nic30 travis-ci pending completion   set done
590 replace_Verilog2001_with_sv2017 rm verbose from coveralls-lcov, outputs is beyolond the travis limit push Nic30 travis-ci pending completion   set done
582 sv2017 fix "" -> <> include paths push Nic30 travis-ci pending completion   set done
581 sv2017 vhdl: rewrite expr. to direct left rec. to reduce codebase push Nic30 travis-ci pending completion   set done
580 sv2017 vhdl: optimize "name" rule push Nic30 travis-ci pending completion   set done
579 sv2017 verilator tests: mark t_lint_incabspath as should_fail push Nic30 travis-ci pending completion   set done
578 sv2017 verilog preproc: DEFAULT_MAX_MACRO_CALL_STACK_SIZE = 128 because of win. push Nic30 travis-ci pending completion   set done
577 sv2017 cleanup push Nic30 travis-ci pending completion   set done
576 sv2017 test refactoring: extract shared code from external test executors push Nic30 travis-ci pending completion   set done
575 sv2017 add vunit as a submodule for tests push Nic30 travis-ci pending completion   set done
574 sv2017 yosys testsuite: integrate to main test suite push Nic30 travis-ci pending completion   set done
572 sv2017 test cleanup: rm duplicit code push Nic30 travis-ci pending completion   set done
571 sv2017 Merge branch 'sv2017' of https://github.com/Nic30/hdlConvertor.git into sv2017 Conflicts: tests/all.py push Nic30 travis-ci pending completion   set done
570 sv2017 add verilator testsuite push Nic30 travis-ci pending completion   set done
569 sv2017 verilator test suite runner push Nic30 travis-ci pending completion   set done