leonardt / verilogAST-cpp / 548

Builds Branch Commit Type Ran Committer Via Coverage
548 simplify-regex Simplify ID sanitize logic Instead of performing the map lookup and regex every time we call toString, instead just do it once when creating the ID node. This should improve performance for code that uses toString multiple times for identifiers ... push leonardt travis-ci-com pending completion   set done
547 prevent-inlining-num-literal Merge 20f0aff5a into a9da41231 Pull #61 web-flow travis-ci-com pending completion   set done
546 prevent-inlining-num-literal Prevents numeric literals from being inlined into index/slice nodes We can inline these into module instance statements, but we can't have something like `(7)[0]` so we prevent inlining of numeric literals into index/slice nodes. push leonardt travis-ci-com pending completion   set done
545 fix-inline-logic-multiple-assign Merge a9da41231 into 8ed06452e Pull #60 web-flow travis-ci-com pending completion   set done
544 fix-inline-logic-multiple-assign Fix handling of multiple assignments in inlining push leonardt travis-ci-com pending completion   set done
543 blacklist-module-instance Merge 8ed06452e into 688ccbab4 Pull #59 web-flow travis-ci-com pending completion   set done
542 blacklist-module-instance Prevent inlining into module instances push leonardt travis-ci-com pending completion   set done
540 fix-inline-slice-logic Add numeric literal case push leonardt travis-ci-com pending completion   set done
541 fix-inline-slice-logic Merge 688ccbab4 into eaa5a43b7 Pull #58 web-flow travis-ci-com pending completion   set done
539 blacklist-module-instance Merge 92370c27e into 0aa25698a Pull #59 web-flow travis-ci-com pending completion   set done
538 blacklist-module-instance Prevent inlining into module instances push leonardt travis-ci-com pending completion   set done
537 prevent-inline-into-module-instance Prevent inlining into module instances push leonardt travis-ci-com pending completion   set done
536 fix-inline-slice-logic Merge 0aa25698a into eaa5a43b7 Pull #58 web-flow travis-ci-com pending completion   set done
535 fix-inline-slice-logic Fix inline blacklist logic for recursive case Before if we had a module such as: ```verilog module test_module ( input [4:0] i1, input [4:0] i2, output [3:0] o0, output [3:0] o1, output [3:0] o2 ); wire [4:0] x; wire [4:0] y; ... push leonardt travis-ci-com pending completion   set done
534 nested-index Merge be216d8cb into eaa5a43b7 Pull #57 web-flow travis-ci-com pending completion   set done